In recent years, thin-film transistors have become used with increasing frequency in numerous applications such as the data-storing elements in high-density SRAMs. As described in, for example, "An Experimental Study on the Short-Channel Effects in Undergated Polysilicon Thin-Film Transistors With and Without Lightly Doped Drain Structures," by Chun Ting Liu and K. H. Lee, IEEE Electronic Device Letters, Vol. 14, No. 3, March 1993, a TFT typically includes a doped amorphous silicon or polysilicon gate formed on an oxide substrate. An oxide layer overlies the gate and an amorphous silicon channel layer overlies the gate oxide layer. The outer extensions of the chemical layer are doped to form drain and source regions. An application of a control voltage to the gate electrode causes electron current flow to occur in the overlying silicon channel layer between the source and drain regions.
In the fabrication of TFTs it has long been the conventional understanding that the polysilicon gate must be wider than the overlying amorphous silicon body or channel layer so that portions of the gate layer extend beyond the longitudinal edges of the silicon film. This is done in order to ensure that the entire amorphous silicon channel layer overlies the underlying gate layer. This design tolerance, which is required in current design rules for fabricating TFTs, increases the spacing between adjacent TFTs and thus increases, for example, the size of the SRAM cell site and reduces integration density.
It is therefore an object of the present invention to provide a TFT having an increased effective channel width.
It is a further object of the present invention to provide a TFT requiring a reduced lateral dimension, thereby increasing integration density in integrated circuits that include such devices.
In accordance with the present invention, the longitudinal edges of the overlying amorphous silicon channel layer of a thin-film transistor are substantially aligned with the longitudinal edges of the underlying polysilicon gate layer. As a result of this line-on-line arrangement of the channel and gate layer, integration area of the transistor is minimized and the spacing between adjacent transistors can be minimized so that optimum integration density can be achieved. In addition, source-to-drain current is increased as the result of the increased channel width gained from the sidewall section of the polysilicon gate, which may occur as a result of the permissible lateral extension of the body (channel) layer over one longitudinal edge of the channel gate layer due to a misalignment in lithography or processing delta.